A TLM2.0 assertion library with centralized monitoring approach

In recent years, design verification gained importance as a result of ever growing complexity and increasing cost of malfunctioning hardware. This resulted in various approaches for verification. On the other hand, higher abstraction levels introduced to help designer cope with the complexity of the designs. Different or specialized verification methods are needed for each abstraction level. Assertion based verification (ABV) is a well known method of verification that could be used for higher abstraction levels such as transaction level modeling (TLM) as well as older ones like register transfer level (RTL). Designers can define assertions by specific languages or use predefined libraries to verify their designs. In this paper, a library of assertions is presented that could be easily used to verify TLM2.0 designs. They introduce some new capabilities such as timing verification and cross channel verification which has not been presented before.