5V tolerant power clamps for mixed-voltage IC´s in 65nm 2.5V salicided CMOS technology

A cascaded power clamp technique is proposed for mixed-voltage IC´s power pins ESD protection using 65nm 2.5V salicided transistors for dual well processes. The effective power-to-ground cascade ESD clamp circuits for mixed 2.5V and 5V powers have been designed to provide low-impedance path between mixed powers and ground lines of IC during the ESD stress. The stacked power clamp also can be used only for 5V power supply without any electrical overstress on transistors. The discussed ESD protection method is easy simulate able and allow having predictable HBM ESD level. The HBM level of this clamp is up to 5kV with allowable layout area.