FPGA implementation of radix 2 division with over-redundant quotient selection

Author

Ibrahem, Attij A. ; Elsimary, Hamed ; Salama, Aly E.

Author_Institution

Electron. Res. Inst., Cairo, Egypt

fYear

2003

fDate

9-11 Dec. 2003

Firstpage

269

Lastpage

273

Abstract

The flexibility of field programmable gate arrays (FPGAs) can provide arithmetic intensive applications with the benefites of custom hardware but without the high cost of custom silicon implementations. In this paper present the adaptation of radix 2 division algorithm for lookup table based FPGAs implementation. This division algorithm is well suited for IEEE 754 standard operands belonging to the range. The implementation has been done with xilinx technology and FPGA-Advantage CAD tools.

Keywords

CAD; IEEE standards; digital arithmetic; field programmable gate arrays; table lookup; FPGA implementation; FPGA-advantage CAD tools; IEEE 754 standard operands; arithmetic intensive applications; custom hardware; custom silicon implementation; field programmable gate arrays; lookup table; over-redundant quotient selection; radix 2 division algorithm; xilinx technology; Application software; Arithmetic; Circuits; Costs; Fabrication; Field programmable gate arrays; Hardware; Logic; Silicon; Table lookup;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronics, 2003. ICM 2003. Proceedings of the 15th International Conference on

Print_ISBN

977-05-2010-1

Type

conf

DOI

10.1109/ICM.2003.1287797

Filename

1287797

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2836565