Fully automated layout generators for high-performance analog VLSI modules

Author

Lee, Ji-Chien ; Gowda, Sudhir M. ; Sheu, Bing J.

Author_Institution

Dept. of Electr. Eng., Univ. of Southern California, Los Angeles, CA, USA

fYear

1989

fDate

22-24 Nov 1989

Firstpage

893

Lastpage

896

Abstract

Algorithms and a software implementation of a fully automated analog layout generation program are described. Device matching, area compaction, and parasitic/noise minimization are the key concerns in the analog layout generation. A new method to incorporate integrated-circuit reliability simulation results into the performance-driven optimization step is also presented. Experimental results on operational amplifiers, voltage comparators, and voltage-controlled oscillators show that the new generation program can produce high-quality circuit layouts efficiently

Keywords

VLSI; circuit layout CAD; circuit reliability; integrated circuit technology; linear integrated circuits; analog VLSI modules; analog layout generation program; area compaction; automated layout generators; device matching; integrated-circuit reliability simulation; operational amplifiers; parasitic/noise minimization; performance-driven optimization step; software implementation; voltage comparators; voltage-controlled oscillators; Circuit noise; Circuit simulation; Compaction; Integrated circuit reliability; Minimization; Noise generators; Optimization methods; Software algorithms; Very large scale integration; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

TENCON '89. Fourth IEEE Region 10 International Conference

Conference_Location

Bombay

Type

conf

DOI

10.1109/TENCON.1989.177075

Filename

177075