Verification of register transfer level (RTL) designs

Author

Pawlovsky, Alberto Palacios ; Naito, Sachio

Author_Institution

Central Res. Lab., Hitachi Ltd., Tokyo, Japan

fYear

1991

fDate

26-27 Sep 1991

Firstpage

30

Lastpage

35

Abstract

The authors´ verification method is based on the translation of the specification and design representation to graph models, where the nodes and edges have a symbolic representation. These labeled graphs are then simplified and by solving the all node-pair path expression problem for them, a pair of regular expressions is obtained for every two nodes in the graphs. The verification is carried out by checking whether or not every pair of regular expressions of the specification has a corresponding one in the design

Keywords

formal verification; graph theory; logic circuits; logic design; all node-pair path expression problem; design representation; design verification; graph models; labeled graphs; register transfer level; regular expressions; specification representations; symbolic representation; Circuit faults; Circuit simulation; Circuit testing; Cost function; Formal verification; Hardware design languages; Integrated circuit technology; Integrated circuit testing; Laboratories; System testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Fault Tolerant Systems, 1991. Proceedings., Pacific Rim International Symposium on

Conference_Location

Kawasaki

Print_ISBN

0-8186-2275-X

Type

conf

DOI

10.1109/{RFTS.1991.212969

Filename

212969