DocumentCode
2839514
Title
A survey on mixed operating mode/self synchronization
Author
Marathe, D.S.
Author_Institution
Electron. & Telecommun. Dept., A.C. Patil Coll. of Eng., Navi Mumbai, India
fYear
2012
fDate
12-13 Nov. 2012
Firstpage
1
Lastpage
3
Abstract
Mixed Operating Mode (MOM) is a digital hardware system which utilizes the advantages of Synchronous and Asynchronous Sequential circuit. But, an Asynchronous sequential circuit suffers from essential hazard. Earlier there were two design philosophies: by the addition of delay elements to the state output, or by input gate modification. These approaches make the whole design slower. On the other hand, the latter approach is based on the assumption that the gate delays are always higher than any wire delay present in the network, but in VLSI circuits the above assumption may not be true and also GALS (Globally Asynchronous, Locally Synchronous)FPGA model has a major drawback of implementing AI(Asynchronous Interfaces) in FPGA devices. AI design style which is based on asynchronous controllers that provides communication between modules(called ports) subject to essential hazard. Using the concept of MOM results in not only saving the logic but also uses less power and making the whole design faster and more flexible. It also improves the throughput and reducing the latency, by satisfying the essential signal condition, this method is capable of providing robust ports, i.e. essential-hazard-free.
Keywords
VLSI; asynchronous circuits; delays; field programmable gate arrays; sequential circuits; synchronisation; AI design; GALS-FPGA model; MOM; VLSI circuits; asynchronous controllers; asynchronous interfaces; asynchronous sequential circuit; delay elements; digital hardware system; gate delays; globally asynchronous-locally synchronous FPGA model; mixed operating mode-self synchronization; signal condition; synchronous sequential circuit; wire delay; Abstracts; Clocks; Delay; Facsimile; Moment methods; Synchronization; Very large scale integration; AI; FPGA; GALS; VLSI;
fLanguage
English
Publisher
ieee
Conference_Titel
NORCHIP, 2012
Conference_Location
Cpenhagen
Print_ISBN
978-1-4673-2221-8
Electronic_ISBN
978-1-4673-2222-5
Type
conf
DOI
10.1109/NORCHP.2012.6403150
Filename
6403150
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