Interactive Generalized Semi Markov Process Model for Evaluating Arbitration Schemes of SoC Bus Architectures

Ever increasing component counts of a system-on-chip makes communication among components complex and diverse. Thus communication architecture becomes a major performance determining candidate. This paper proposes a formal technique for system level performance analysis that can help the designer to select the appropriate arbitration scheme for a chosen bus-based communication architecture. For a bus with arbitration, we formulate a model based on interacting generalized semi Markov process. We mainly focus on building model for single shared bus architecture and explore arbitration along with different priority schemes viz. (i) fixed, (ii) lottery based and (iii) round robin. We describe the model of bus architecture using these arbitration schemes in the stateflow component of MATLAB. Our modeling approach provides an evaluation and comparison of performance parameters viz. memory bandwidth, processing element utilization, average queue length at the memory and average waiting time seen by a processing element, for a chosen arbitration scheme.