Processor architectures for fault tolerant avionic systems

Author

Smith, T.J. ; Yelverton, J. Ned

Author_Institution

IBM Corp., Houston, TX, USA

fYear

1991

fDate

14-17 Oct 1991

Firstpage

213

Lastpage

219

Abstract

The authors consider the application of modern processor architectures to avionics systems requiring fault masking during critical flight dynamic phases such as ascent or entry. Fault masking implies uninterrupted control during the period of fault detection, identification and recovery (FDIR). To provide this uninterrupted control requires tight coordination between redundant processors. The impact of the requirement for fault masking capability through tightly coupled processors on modern processor architectures is discussed

Keywords

aircraft instrumentation; computer architecture; computerised instrumentation; fault tolerant computing; redundancy; system recovery; ascent; coupled processors; critical flight dynamic phases; cross strapped commander listener; entry; fault detection; fault masking; fault tolerant avionic; identification; n-modular redundant architecture; processor architectures; recovery; redundant processors; two round exchange; uninterrupted control; Aerospace electronics; Computer architecture; Fault detection; Fault tolerance; Fault tolerant systems; Hardware; Modems; Nuclear magnetic resonance; Space vehicles; Synchronization;

fLanguage

English

Publisher

ieee

Conference_Titel

Digital Avionics Systems Conference, 1991. Proceedings., IEEE/AIAA 10th

Conference_Location

Los Angeles, CA

Type

conf

DOI

10.1109/DASC.1991.177169

Filename

177169