Determining error rate in error tolerant VLSI chips

In the near future all die implementing high performance circuitry will contain hundreds of thousands of defects. Most companies will attempt to achieve useful levels of functionally good die using classical and enhanced fault tolerant and defect tolerant techniques. We advocate a new notion for yield enhancement called error tolerance that includes marketing chips that occasionally output errors. The quantity and quality of errors produced by a chip can be characterized several ways, such as by accuracy, error rate, and accumulation (retention). This paper focuses on test techniques for estimating error rate.