Performance evaluation of direct form FIR filter with merged arithmetic architecture

This paper demonstrates a novel design concept and optimization method towards the design of low power FIR filters for a fixed coefficient set. The prowess of merged arithmetic architecture is capitalized in the direct form filter structure to avoid the total number of accumulators and the lengths of the registers from being increased progressively with the filter taps. A delay profile driven adder is designed to further exploit the uneven signal arrival time at the final stage of the Carry Save Adder (CSA) tree. The performance of the proposed filter structure has been evaluated by comparing its prototype with two other optimized transposed direct form filter designs, implemented with the same process technology.