DocumentCode
2842843
Title
Evaluation and reduction of simulation error of chip-to-chip signal delay
Author
Ohshima, Takayuki ; Nonaka, Junpei ; Yamada, Itsui ; Ohno, Tsuyoshi ; Isozaki, Tomoald ; Hachiya, Kotaro
Author_Institution
NEC Electron. Corp., Kawasaki, Japan
fYear
2005
fDate
24-26 Oct. 2005
Firstpage
163
Lastpage
166
Abstract
This paper proposes an evaluation method of an error between measurement and simulation of chip-to-chip signal delay. It also presents a method to reduce the delay error in the simulation using IBIS model. In our example measurement and simulation by the proposed method, chip-to-chip delay error is 22 % (87ps) and delay errors in each segment (core logic cell, input/output buffer, package, board) are also obtained.
Keywords
buffer circuits; circuit simulation; delays; integrated circuit measurement; integrated circuit modelling; 87 ps; IBIS model; chip-to-chip delay error; chip-to-chip signal delay; core logic cell; input/output buffer; simulation error evaluation; Analytical models; Circuit simulation; Jitter; Logic; Oscilloscopes; Packaging machines; Propagation delay; Semiconductor device measurement; Timing; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Electrical Performance of Electronic Packaging, 2005. IEEE 14th Topical Meeting on
Print_ISBN
0-7803-9220-5
Type
conf
DOI
10.1109/EPEP.2005.1563727
Filename
1563727
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