PVT-tolerant 7-Transistor SRAM Optimization via Polynomial Regression

Low power consumption, stability, and PVT-tolerance in Static Random Access Memories (SRAM) is essential for nanoscale System-on-Chip (SoC) designs. In this paper, a novel design flow is presented for optimizing a figure of merit called Power to Static-Noise-Margin (SNM) Ratio (PSR). The minimization of PSR results in power minimization and SNM maximization of nano-CMOS SRAM circuits which are mutually conflicting objectives. A 45 nm single ended 7-Transistor SRAM is used as an example circuit for demonstrating the effectiveness of the optimal design flow presented in this paper. Worst case temperature analysis is performed on a baseline SRAM circuit for all three Figures of Merit (FoMs): power, SNM, and PSR. After accurate characterization of the FoMs for worst case temperature and process variation analysis, the baseline SRAM circuit at worst case temperature is subjected to a polynomial regression based optimization algorithm. Simulation results demonstrate that the optimal SRAM design is PVT-tolerant with optimized power consumption, SNM and PSR.