A Novel 14-Transistors Low-Power High-Speed PPM Adder

Author

Tripathi, Ramracksha ; Mishra, Shivshankar ; Prakash, S.G.

Author_Institution

Dept. of Electron. & Commun. Eng., Univ. of Allahabad, Allahabad, India

fYear

2011

fDate

19-21 Dec. 2011

Firstpage

124

Lastpage

128

Abstract

In this paper we mainly deal with design and simulation of different redundant-binary full adder (Plus-Plus-Minus Adder) topologies using minimum number of transistors. These PPM adder topologies are simulated to evaluate their performance in total power dissipation, speed, and PDP. Compared with other PPM adder designs, the proposed novel design full adder topology features higher computing speed and lower energy (power delay product) operation. The simulation results reveal that the overall PDP for the proposed circuits have been improved by 10% to 15% at the supply voltage of 1.8V when compared with the reported PPM adder topologies at 0.18μm CMOS technology.

Keywords

CMOS logic circuits; adders; network topology; redundant number systems; CMOS technology; higher computing speed; novel 14-transistors low-power high-speed PPM adder; plus-plus-minus adder topology; power dissipation; redundant-binary full adder topology; voltage 1.8 V; Adders; CMOS integrated circuits; Delay; Power demand; Topology; Transistors; Very large scale integration; CMOS logic; PPM adder; high-speed; low-power; redundant binary adder;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronic System Design (ISED), 2011 International Symposium on

Conference_Location

Kochi, Kerala

Print_ISBN

978-1-4577-1880-9

Type

conf

DOI

10.1109/ISED.2011.19

Filename

6117338