Investigation of Se ion implantation for GaAs very high speed gate array

Author

Jianghong, Zhang ; Macheng, Song ; Hao Jingchen ; Yaguang, Lian

Author_Institution

Nat. Key Lab. of ASIC, Hebei, China

fYear

1998

fDate

1998

Firstpage

714

Lastpage

717

Abstract

Se⁺-implanted GaAs substrates were performed at room temperature. We investigated the effects of incident energy, the ion dose and the incident angle. The rapid thermal annealing (RTA) temperature and the duration time as well as all these parameter were optimized. Using Se⁺-implantation at the dose of 1×10 ¹³ cm^-2, we got the n⁺-type thin layers on GaAs substrates. The carrier mobility was 3010 cm²/v.s, and the impurity activity is greater than 74%. The Se⁺ implanted GaAs substrates were successfully used in the fabrication of 3K-gates GaAs gate array

Keywords

III-V semiconductors; MESFET integrated circuits; carrier mobility; gallium arsenide; integrated circuit technology; ion implantation; logic arrays; rapid thermal annealing; selenium; very high speed integrated circuits; GaAs very high speed gate array; GaAs:Se; MESFET IC; Se ion implantation; carrier mobility; impurity activity; rapid thermal annealing; Fabrication; Gallium arsenide; Impurities; Integrated circuit technology; Ion implantation; Laboratories; Logic arrays; MESFETs; Rapid thermal annealing; Temperature;

fLanguage

English

Publisher

ieee

Conference_Titel

Microwave and Millimeter Wave Technology Proceedings, 1998. ICMMT '98. 1998 International Conference on

Conference_Location

Beijing

Print_ISBN

0-7803-4308-5

Type

conf

DOI

10.1109/ICMMT.1998.768389

Filename

768389