Simultaneous switching noise in CMOS VLSI circuits

In this paper, we present techniques for estimating the worst-case voltage variations in the power distribution network due to switching of I/O buffers or internal logic circuits in a small time interval. We refer to these voltage variations as the simultaneous switching noise (SSN). We present simulation results to show that a relative skew in the switching time can dramatically increase the SSN due to I/O buffers with dissimilar loads. We also present a constraint graph based technique that accounts for logic dependencies between switching elements to obtain accurate estimates of the worst-case SSN due to internal logic circuits. Comparisons with SPICE simulations are presented to validate our approach