Advanced CMOS Technology beyond 45nm Node

Author

Kawanaka, Shigeru ; Hokazono, Akira ; Yasutake, Nobuaki ; Tatsumura, Kosuke ; Koyama, Masato ; Toyoshima, Yoshiaki

Author_Institution

Center for Semicond. Res. & Dev., Yokohama

fYear

2007

fDate

23-25 April 2007

Firstpage

1

Lastpage

4

Abstract

At the time of CMOS device development in 45 nm node, newly developed materials and techniques have been discussed and experimented to achieve power-performance requirement. Based on the published reports, the overview of current 45 nm node technology development status is summarized. Then, the prevision of 32 nm node device design strategy is discussed considering key technologies such as stress enhancement technique, metal high-k gate stack and non-classical device scaling both for structure and temperature.

Keywords

CMOS logic circuits; Ge-Si alloys; carrier mobility; dielectric materials; high-k dielectric thin films; integrated circuit technology; large scale integration; stress analysis; CMOS device development; CMOS technology; LSI; Si-Ge; logic CMOS device; metal high-k gate stack scaling; node technology development status; nonclassical device scaling; power-performance requirement; size 45 nm; stress enhancement technique; CMOS technology; Compressive stress; Geometry; Germanium silicon alloys; High K dielectric materials; High-K gate dielectrics; Insulation; Large scale integration; Silicon germanium; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, Systems and Applications, 2007. VLSI-TSA 2007. International Symposium on

Conference_Location

Hsinchu

ISSN

1524-766X

Print_ISBN

1-4244-0584-X

Electronic_ISBN

1524-766X

Type

conf

DOI

10.1109/VTSA.2007.378967

Filename

4239535