A 65nm 1.2V 16-bit audio codec sigma-delta ADC in 2-2 MASH architecture with temperature-compensated biasing

Author

Choi, Thomas ; Lam, Brian

Author_Institution

IC Design Group, Hong Kong Appl. Sci. & Technol. Res. Inst. Co. Ltd., Shatin, China

fYear

2011

fDate

17-18 Nov. 2011

Firstpage

1

Lastpage

2

Abstract

A 16-bit audio codec sigma-delta (Σ-Δ) ADC including a decimation filter, implemented in a 65nm process, is reported measured results. The ADC operates with a 1.2V supply voltage and a 256 times over-sampling, achieving a Spurious-free Dynamic Range (SFDR) of 70dB. The 2-2 MASH architecture has been employed to reduce the required capacitor ratio for improved matching. A temperature compensation scheme is also included in the biasing circuit to limit the power consumption at high temperatures.

Keywords

CMOS integrated circuits; capacitors; codecs; filters; sigma-delta modulation; 2-2 MASH architecture; SFDR; audio codec Σ-Δ ADC; audio codec sigma-delta ADC; capacitor ratio; decimation filter; gain 70 dB; nanoscale CMOS process; power consumption; size 65 nm; spurious-free dynamic range; temperature-compensated biasing circuit; voltage 1.2 V; word length 16 bit; Capacitors; Multi-stage noise shaping; Quantization; Semiconductor device measurement; Signal to noise ratio; Temperature measurement; 1.2V; 65nm; ADC; MASH; Sigma-delta; temperature compensation;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices and Solid-State Circuits (EDSSC), 2011 International Conference of

Conference_Location

Tianjin

ISSN

Pending

Print_ISBN

978-1-4577-1998-1

Electronic_ISBN

Pending

Type

conf

DOI

10.1109/EDSSC.2011.6117639

Filename

6117639