Scheduling and hardware sharing in pipelined data paths

A scheduling and hardware sharing algorithm is presented. This algorithm is generic and can be used for synthesizing both nonpipelined and pipelined data paths. The scheduling algorithm tries to distribute operations equally among partitions to maximize hardware sharing. Multiplexer delays are explicitly considered to produce a more accurate scheduling. In hardware sharing, structural parameters such as the size of multiplexers, interconnect overhead, the size of the smallest sharable operator etc. are used to control the amount of sharing globally and produce a heuristically optimized RTL structure. The scheduling algorithm is iterated until a satisfactory structure is obtained. The algorithm also can be used for partitioning a large system into implementable pieces. The algorithm has been used successfully for synthesizing a pipelined data path from a graphics processing description that contains about 1000 components.<>