DocumentCode
2850372
Title
On the design of easily testable and reconfigurable systolic arrays
Author
Kim, Jung H.
Author_Institution
Center for Adv. Comput. Studies, Southwestern Louisiana Univ., Lafayette, LA, USA
fYear
1988
fDate
25-27 May 1988
Firstpage
505
Lastpage
514
Abstract
Methods to design easily testable and reconfigurable (ETAR) systolic arrays are proposed, and procedures to design linear unidirectional and bidirectional systolic arrays are given. The main feature of the proposed designs is that the processing elements in liner arrays can all be tested simultaneously, thus reducing the testing time significantly. Another feature is that the throughputs of the reconfigured linear unidirectional as well as bidirectional arrays can equal those of the fault-free linear arrays
Keywords
cellular arrays; circuit CAD; fault tolerant computing; integrated circuit testing; ETAR systolic arrays; bidirectional systolic arrays; fault-free linear arrays; linear unidirectional systolic arrays; reconfigurable systolic arrays; testable systolic arrays; throughputs; Clocks; Costs; Degradation; Design methodology; Fault detection; Fault tolerance; System testing; Systolic arrays; Throughput; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Systolic Arrays, 1988., Proceedings of the International Conference on
Conference_Location
San Diego, CA
Print_ISBN
0-8186-8860-2
Type
conf
DOI
10.1109/ARRAYS.1988.18087
Filename
18087
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