Double Enhance Dielectric Layer Electric Field high voltage SOI LDMOS

Author

Yang, X.M. ; Zhang, B. ; Luo, X.R.

Author_Institution

State Key Lab. of Electron. Thin Films & Integrated Devices, Univ. of Electron. Sci. & Technol. of China, Chengdu, China

fYear

2011

fDate

17-18 Nov. 2011

Firstpage

1

Lastpage

2

Abstract

A Double Enhance Dielectric Layer Electric Field (Double ENDIF) silicon-on-insulator (SOI) LDMOS is proposed for high breakdown voltage (BV). The electric field in the buried oxide at the source and drain sides is enhance by charges in shield-trench at positive back-gate bias, resulting to improve the B V. The electric characteristic of the new structure is research by 2D MECICI. Simulation result shows that BV of the new structure reaches 1025 V at 4μm and 1μm thickness of the silicon and buried oxide layers respectively.

Keywords

MOSFET; buried layers; semiconductor device breakdown; silicon-on-insulator; 2D MECICI; BV; breakdown voltage; buried oxide layers; double ENDIF silicon-on-insulator LDMOS; double enhance dielectric layer electric field high voltage SOI LDMOS; electric characteristic; positive back-gate bias; shield-trench; size 1 mum; size 4 mum; source and drain sides; Dielectrics; Educational institutions; Electric breakdown; Electric fields; Silicon; Silicon on insulator technology; Three dimensional displays; Back-gate; breakdown voltage; double enhance dielectric layer electric field; p-type layer; shield-trench; silicon-on-insulator LDMOS;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices and Solid-State Circuits (EDSSC), 2011 International Conference of

Conference_Location

Tianjin

ISSN

Pending

Print_ISBN

978-1-4577-1998-1

Electronic_ISBN

Pending

Type

conf

DOI

10.1109/EDSSC.2011.6117731

Filename

6117731