Global refinement for building block layout

A global optimization method with global wiring refinement for building block placement is proposed. The method is based on the notion of a vertex decomposed digraph, called the mixed graph model, which has both orientable edges and directed edges to reflect global routing information and its modification. Global wiring is estimated in terms of chip area and is to be optimized. The graph model is proved to be determinant and legal. A nonconflict precise vertex decomposition (PVD) method is described, and a global wiring refinement method is presented together with a topological bottleneck model. Promising results were obtained in several runs on practical examples.<>