Gate delay ratio model for unified path delay analysis

A new paradigm of path delay analysis is proposed against increasing process variation. A simple yet effective model - gate delay ratio model (GDRM) - is introduced to analyze the path delays of production devices without modifying device circuits and ATE systems. Curve fitting of the power voltage dependence of a delay on GDRM obtains the wire delay, gate delay, and threshold voltage of the transistors of the gates in a path. The new paradigm is verified by the evaluation of scan tests, SRAM MBISTs, ring oscillators, and SRAM test chips, which were fabricated by the 130, 90, and 65 nm devices of three companies. The analysis of parametric failures based on the proposal is demonstrated on thermal inversion failures. The verification and demonstration indicate the possibility of the new paradigm to coordinate design, manufacturing, characterization, and testing to reduce process variations and parametric defects.