• DocumentCode
    2853186
  • Title

    Evaluation of sSOI wafers for 22nm node and beyond

  • Author

    Allibert, F. ; Cheng, K. ; Vinet, M. ; Schwarzenbach, W. ; Khakifirooz, A. ; Ecarnot, L. ; Nguyen, B.Y. ; Doris, B.

  • Author_Institution
    Soitec, Crolles, France
  • fYear
    2012
  • fDate
    1-4 Oct. 2012
  • Firstpage
    1
  • Lastpage
    2
  • Abstract
    We assessed the performance of planar fully-depleted transistors built on sSOI wafers by comparing them to devices fabricated with the same process on SOI. A 23% increase in device performance was demonstrated, while maintaining at least as good device electrostatics and matching as SOI.
  • Keywords
    MOSFET; silicon-on-insulator; FD transistor technology; SOI wafer evaluation; planar fully-depleted transistor technology; size 22 nm; Electrostatics; Logic gates; Performance evaluation; Silicon; Strain; Voltage measurement;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    SOI Conference (SOI), 2012 IEEE International
  • Conference_Location
    NAPA, CA
  • ISSN
    1078-621X
  • Print_ISBN
    978-1-4673-2690-2
  • Electronic_ISBN
    1078-621X
  • Type

    conf

  • DOI
    10.1109/SOI.2012.6404397
  • Filename
    6404397
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2853186