DocumentCode
2853982
Title
Modeling for computation of IC-gate yield from processing data
Author
Wilson, C. ; Dowell, R.
Author_Institution
Bell Telephone Labs., Inc., Murray Hill, N.J., USA
Volume
XV
fYear
1972
fDate
16-18 Feb. 1972
Firstpage
68
Lastpage
69
Abstract
Modeling techniques allowing computation of IC-gate electrical yield from processing distributions and circuit configuration will be presented. An example will include an analysis of a Collection-Diffused-Isolated IC gate.
Keywords
Circuit analysis; Circuit analysis computing; Computational modeling; Conductivity; Doping; Gain measurement; Impurities; Semiconductor process modeling; Solid state circuits; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference. Digest of Technical Papers. 1972 IEEE International
Conference_Location
Philadelphia, PA, USA
Type
conf
DOI
10.1109/ISSCC.1972.1155094
Filename
1155094
Link To Document