A binary logic synthesis approach to the bit-level implementation of generalized rank-order filters

A binary logic synthesis approach is presented for the bit-level implementation of generalized rank-order filters. It is shown that rank-order filters can be realized directly from the binary weighted signal by using combinational logic circuits. A pipelined architecture based on the algorithm is also introduced. The realization is simple and modular in structure and suitable for VLSI implementation, and no threshold decomposition and reconstruction circuits are needed. Only one type of basic cell is employed. K basic cells connected together will perform K-bit rank-order filtering. The proposed filter has flexibility for various applications. Considering the proposed architecture as a building block, recursive rank-order filters, 2-D rank-order filters, and adaptive rank-order filters can easily be realized