Pipelining method without global communications for relaxation-based processor

Describes a hardware which accelerates relaxation-based circuit analysis: Sophia relaxation-based accelerating processor (SRAP). Unlike other multiprocessors, SRAP does not share subcircuits with the corresponding processor elements (PEs), but each PE calculates all nodes of the circuit. For this processor the authors extend Gauss-Siedel (GS) calculation such that each PE works as a pipeline. The method considered requires no global communications between PEs except for the convergence decision and initial set ups. The method is well suited for massively parallel processing. To calculate all nodes of the circuit it requires more memory than conventional multiprocessors, but its communication cost will be cheaper. Additionally, the authors use a SPICE-based relaxation circuit analyzer-SRP (Sophia relaxation program), and evaluate accelerating ratios for ECL (emitter coupled logic), TTL (transistor transistor logic), CMOS adder, and NMOS SRAMs. Four to five times speedup with 8 PEs is achieved. For a ladder or mesh circuit which is represented by the differential Laplace equation, almost linear characteristics of multiprocessor speedup are achieved