Stability and scaling of double loop ΣΔ modulators

The application of the double loop ΣΔ modulator to analog-to-digital conversion is considered. To avoid integrator saturation in implementations, it is necessary to know the maximum occurring integrator output voltages. The authors address this problem by deriving upper bounds on the steady-state values of integrator outputs for the general double loop modulator with constant inputs. They use the upper bounds to derive scaling factors that are optimized with respect to stability as well as an approximate performance measure. Simulations show that the results which are proven for constant inputs can be useful in the design of modulators with dynamic inputs, and that gains of about 2 dB in both dynamic range and peak signal-to-noise ratio can be achieved for time-varying inputs