A fault tolerant journalized stack processor architecture

Dependable architectures play an important role in many areas that impact our lives. Dependability is achieved by using a set of analysis and design techniques that increases the complexity and consequently the cost of systems. In this paper, to meet low cost requirement of IP cores, we propose a simple dependable stack processor architecture using a re-execution model of instructions in the case of error detection in consecutive sequences of instructions execution. The architecture is based on applying two memory journals as intermediate stages between processor and main memory in write operations. Then, we present the results obtained by using the developed emulation tools.