VLSI architecture for a convolution-based DCT in residue arithmetic

Author

Wolter, S. ; Klaassen, R. ; Birreck, D. ; Laur, R.

Author_Institution

Inst. fuer Mikroelektronik, Bremen Univ., Germany

Volume

5

fYear

1992

fDate

10-13 May 1992

Firstpage

2108

Abstract

A new high speed discrete cosine transform (DCT) architecture based on a cyclic convolution and residue arithmetic is introduced. The approach uses the two step DCT algorithm of P. Duhamel and H. H´Mida (1987). The first step is a cyclic convolution. It is followed by a multiplication with a matrix filled with 0 and ±1. This algorithm is realized in residue arithmetic. Because the residue arithmetic is carry-free and the chosen DCT algorithm allows a hardware implementation with local interconnections and great regularity, the proposed architecture for an 8×8 DCT can reach throughput rates over 150 MSamples/s, which meets the requirements for HDTV applications. The concept has been confirmed by simulations using a hardware description language

Keywords

VLSI; digital arithmetic; discrete cosine transforms; high definition television; image processing; HDTV applications; VLSI architecture; convolution-based DCT; cyclic convolution; discrete cosine transform; hardware description language; hardware implementation; local interconnections; residue arithmetic; throughput rates; Arithmetic; Circuit simulation; Convolution; Convolutional codes; Data compression; Discrete cosine transforms; HDTV; Hardware design languages; Throughput; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1992. ISCAS '92. Proceedings., 1992 IEEE International Symposium on

Conference_Location

San Diego, CA

Print_ISBN

0-7803-0593-0

Type

conf

DOI

10.1109/ISCAS.1992.230577

Filename

230577