DocumentCode
2859371
Title
A 1024-bit MNOS RAM using avalanche-tunnel injection
Author
Uchida, Yasuo ; Norio Endo ; Saito, Sakuyoshi ; Konaka, M. ; Nojima, I. ; Nishi, Yoshio ; Tamaru
Author_Institution
Toshiba Res. and Dev. Ctr., Kanagawa, Japan
Volume
XVIII
fYear
1975
fDate
27426
Firstpage
108
Lastpage
109
Abstract
This effort will describe a fully-decoded 1024-bit non-volatile MNOS RAM. Writing 0 and 1 is possible using avalanche-tunneling and direct tunneling, respectively, by coincident selection without isolation between memory array and peripheral circuits.
Keywords
Chemical technology; Circuits; Decoding; MOSFETs; Nonvolatile memory; Random access memory; Read-write memory; Silicon; Threshold voltage; Writing;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference. Digest of Technical Papers. 1975 IEEE International
Type
conf
DOI
10.1109/ISSCC.1975.1155439
Filename
1155439
Link To Document