Using verification technology for validation coverage analysis and test generation

Despite great advances in Formal Verification (FV) simulation is still the primary means for design validation. The definition of pragmatic measures for the coverage achieved and the problem of automatic test generation (ATG) are of great importance. In this paper we introduce a new set of metrics, the Event Sequence Coverage Metrics (ESCMs). Our approach is based on an automatic method to extract the control flow of a circuit which can be explored for coverage analysis and ATG. We combine FV and traditional ATPG techniques to automatically generate sequences which traverse uncovered parts of the control graph or exercise uninstantiated control event sequences