DocumentCode
2859964
Title
Low cost partial scan design: a high level synthesis approach
Author
Flottes, M.L. ; Pires, R. ; Rouzeyre, B. ; Volpe, L.
Author_Institution
Lab. d´´Inf., de Robotique et de Micro-Electron., CNRS, Montpellier, France
fYear
1998
fDate
26-30 Apr 1998
Firstpage
332
Lastpage
340
Abstract
In this paper, we present a high level synthesis method for partial scan designs. High level testability information are used to guide the synthesis process towards designs with a minimal number of scan registers. The maximal fault coverage is achievable for these designs. This method mainly leans on ad-hoc modifications of the register allocation process
Keywords
design for testability; fault diagnosis; high level synthesis; logic design; logic testing; high-level synthesis; high-level testability information; low-cost partial scan design; maximal fault coverage; register allocation process; Automatic test pattern generation; Controllability; Costs; Delay; High level synthesis; Observability; Open loop systems; Pins; Robots; Testing;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Test Symposium, 1998. Proceedings. 16th IEEE
Conference_Location
Monterey, CA
ISSN
1093-0167
Print_ISBN
0-8186-8436-4
Type
conf
DOI
10.1109/VTEST.1998.670887
Filename
670887
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