A sense amplifier for a low clock capacitance 16K CCD memory

TO AVOID the problems associated with the large clock capacitance of synchronous, multiphase CCD memory organizations, a 16,384-bit CCD memory chip´ has bcen designed,using a new clocking approach. This memory has one phase biased to an intermediate voltage, while the other phase is clocked to higher and lower potentials. The principle rcduction in clock capacitance is achieved by organizing the memory as a Line Addressable Random Access Memory (LARAM). Since in this organization only one line is clocked at any one time,the lines in a block share a common input bus @x and a common sense amplifier.