Cycle Accurate Verification of Synchronous Sequential Circuit Specified with UML 2.0 Modelling

The surging complexity of modern embedded systems has been imposing challenges to designers since last decade. It is generally agreed that an approach to taming the complexity is to properly raise the level of abstraction to that of system-level designs. The Unified Modelling Language (UML) is considered appropriate to specify abstract systems. To support the gap between UML and low level hardware descriptions, a few pilot tools and methodologies were proposed by both the EDA community and the academia. However, these tools either lack support for cycle accurate system specifications in UML or ignore the efficiency issue in cycle accurate system specifications based on UML. In this paper, an improved method is proposed to efficiently specify systems at cycle accuracy by significantly simplifying clock control modelling. This method is further supported by an improved translator to convert UML 2.0 specifications into executable SystemC descriptions. We believe that our method would be a significant contribution to the electronic system level (ESL) tools.