DocumentCode
2865543
Title
A 100ns 150mW 64Kbit ROM
Author
Wilson, D. ; Schroeder, P.
Author_Institution
Mostek, Inc., Carrollton, TX, USA
Volume
XXI
fYear
1978
fDate
15-17 Feb. 1978
Firstpage
152
Lastpage
153
Abstract
A sub 100ns 64K ROM using standard N-channel silicon-gate technology will be discussed. The ROM organized as 8K words by 8bits per word operates from a single 5V supply and has a typical access time and power of 80ns and 150mW.
Keywords
Clocks; Data buses; Decoding; Differential amplifiers; Implants; Latches; Read only memory; Silicon; Threshold voltage; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference. Digest of Technical Papers. 1978 IEEE International
Conference_Location
San Francisco, CA, USA
Type
conf
DOI
10.1109/ISSCC.1978.1155829
Filename
1155829
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