• DocumentCode
    2865842
  • Title

    Application of heterodimensional transistors for weighted sum threshold logic operation

  • Author

    Nazimudeen, A.S. ; Deng, J. ; Shur, M.S.

  • Author_Institution
    Dept. of Electr. Comput. & Syst. Eng., Rensselaer Polytech. Inst., Troy, NY, USA
  • fYear
    2000
  • fDate
    2000
  • Firstpage
    101
  • Lastpage
    109
  • Abstract
    In this paper we describe a novel circuit application of the heterodimensional device technology - the Weighted Sum Threshold (WST) Logic Operation which is implemented with novel heterodimensional devices, the Two Dimensional Junction Field Effect Transistors (2D JFETs) and the Resonant Tunneling Diodes (RTDs)
  • Keywords
    JFET circuits; resonant tunnelling diodes; threshold logic; heterodimensional device; resonant tunneling diode; two-dimensional junction field effect transistor; weighted sum threshold logic circuit; Circuit synthesis; HEMTs; JFETs; Logic circuits; Logic devices; MODFETs; RLC circuits; Resonant tunneling devices; Threshold voltage; USA Councils;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    High Performance Devices, 2000. Proceedings. 2000 IEEE/Cornell Conference on
  • Conference_Location
    Ithaca, NY
  • ISSN
    1529-3068
  • Print_ISBN
    0-7803-6381-7
  • Type

    conf

  • DOI
    10.1109/CORNEL.2000.902524
  • Filename
    902524
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2865842