DocumentCode
2866252
Title
Verification of a 32-bit RISC processor core
Author
Kasanko, Tuukka ; Nurmi, Jari
Author_Institution
Inst. of Digital & Comput. Syst., Tampere Univ. of Technol., Finland
fYear
2004
fDate
16-18 Nov. 2004
Firstpage
107
Lastpage
110
Abstract
Verification is currently the most time consuming task in the development of new designs. Automation must be introduced in order to achieve satisfactory results within reasonable time. This work presents how verification was conducted for one SoC component, a 32-bit RISC processor core. A wide variety of tools and methods were used in the process.
Keywords
circuit CAD; integrated circuit design; logic CAD; reduced instruction set computing; system-on-chip; 32 bit; RISC processor core design verification; SoC component; design automation; verification methods; verification time; verification tools; Automatic testing; Automation; Documentation; Microprocessors; Personnel; Real time systems; Reduced instruction set computing; Registers; System testing; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
System-on-Chip, 2004. Proceedings. 2004 International Symposium on
Print_ISBN
0-7803-8558-6
Type
conf
DOI
10.1109/ISSOC.2004.1411161
Filename
1411161
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