Capacitor energy variation based designer-side switching losses analysis for integrated synchronous Buck converters in CMOS technology

This paper introduces a designer-side switching loss analysis characterized by evaluating parasitic capacitor´s energy variation and related losses for integrated synchronous Buck converters in CMOS technology (ISBC). After categorizing losses related to power FET parasitic capacitors´ charging/discharging currents as charging/discharging losses (C_loss), it is noticed that the ratio of charging/discharging losses over capacitor´s energy variation (ROCL) presents two extreme values; one of which is almost 100% and the other one is ignorable. Also, the same capacitor might encounter different ROCL when switching event is different. Five typical kinds of charging/discharging circuits are further classified in terms of ROCL. In order to evaluate parasitic capacitor´s energy variation in a complete switching event, a hypothesis equation is adopted to cope with the variation of capacitance because of the operation mode shift of the power FET. At the same time, a process is introduced about how to verify the hypothesis and extract the unit width variables involved in the energy variation evaluation. The proposed switching losses analysis can provide losses breakdown in terms of semiconductor process technology data. At the same time, the analysis overcomes limitations in previous methods and supports the switching losses analysis for those advanced ISBC utilizing power stage width segmentation technology for the sake of wide load range efficiency. Transistor level simulation in Cadence environment verifies the analysis.