DocumentCode
2867332
Title
A 25ns 4K static RAM
Author
Jecmen, R. ; Ebel, A. ; Smith, R. ; Kynett, V. ; Chi-Hung Hui ; Pashley, R.
Author_Institution
Intel Corp., Santa Clara, CA, USA
Volume
XXII
fYear
1979
fDate
14-16 Feb. 1979
Firstpage
100
Lastpage
101
Abstract
Using device scaling, an N-channel MOS technology has been developed with minimum gate delays of less than 400ps. This paper will report on the design of 5V 1024b and 4096b RAMs with typical access times of 15ns and 25ns, respectively.
Keywords
Added delay; Circuits; Current supplies; Decoding; Emergency power supplies; Power dissipation; Random access memory; Read-write memory; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference. Digest of Technical Papers. 1979 IEEE International
Conference_Location
Philadelphia, PA, USA
Type
conf
DOI
10.1109/ISSCC.1979.1155936
Filename
1155936
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