A novel strategy to test core based designs

This paper proposes a novel technique for testing core based system-on-a-chip (SOC), targeting to reduce the test application time as well as the test hardware. The proposed work is to be done in two parts: (i) Core Level and (ii) Interconnect Level. To date, many authors have studied the problem of testing core-based systems, but not much work exists on testing the cores and the interconnects together. Also proposed is an efficient test access design to reduce test cost by minimising test application time. Test access is a major challenge for testing of core-based system-on-a-chip designs. Several issues related to the Test Access Mechanism (TAM) design such as assignment of cores to test buses, optimal number of buses required, distribution of test data bandwidth between several buses have been handled in this paper. In doing so, the testing time has been found to be drastically reduced at the cost of some extra test hardware