DocumentCode
2868115
Title
CCD architectures for high-speed transient recording
Author
Pocha, M. ; Balch, J. ; McConaghy, C.
Author_Institution
University of California Lawrence Livermore Lab., Livermore, CA, USA
Volume
XXII
fYear
1979
fDate
14-16 Feb. 1979
Firstpage
70
Lastpage
71
Abstract
CCDs using a parallel-serial and serial-parallel-serial architecture for high-speed (> 100MHz)transient recording will be covered.
Keywords
Charge coupled devices; Clocks; Delay lines; Demultiplexing; Electrodes; Frequency; Laboratories; Sampling methods; Shift registers; Silicon;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference. Digest of Technical Papers. 1979 IEEE International
Conference_Location
Philadelphia, PA, USA
Type
conf
DOI
10.1109/ISSCC.1979.1155980
Filename
1155980
Link To Document