DocumentCode
2868690
Title
Degradation of NMOSFETs during high-field injection with reverse biased voltage at source and drain junctions
Author
Jarwal, R.K. ; Misra, D.
Author_Institution
Dept. of Electr. & Comput. Eng., New Jersey Inst. of Technol., Newark, NJ, USA
fYear
2001
fDate
2001
Firstpage
485
Lastpage
490
Abstract
Degradation to threshold voltage Vt and transconductance gm of n-channel MOSFETs due to reverse biased potential at source and drain junctions during high-field electron injection were studied. Both gate injection and substrate injection modes were used to estimate initial oxide traps and breakdown characteristics. During gate injection, stress induced Vt and gm shifts show minimal dependence on the reverse biased floating voltage whereas during substrate injection Vt shifts linearly depend on the floating reverse biased voltage and gm shifts show minimal dependence. An asymmetry in the distribution of electron traps at the gate-oxide and substrate-oxide interfaces was observed. For gate injection the oxide field at breakdown is higher than substrate injection and these field values are independent of reverse biased voltage. Charge to breakdown decreases with reverse biased voltage for gate injection and increases for substrate injection. Moreover, charge to breakdown values for gate injections are smaller than substrate injection
Keywords
MOSFET; electron traps; semiconductor device breakdown; semiconductor device models; semiconductor device reliability; NMOSFETs; breakdown characteristics; charge to breakdown; drain junctions; electron traps; gate injection; gate-oxide interface; high-field electron injection; high-field injection; initial oxide traps; oxide field; reverse biased potential; reverse biased voltage; source junctions; substrate injection; substrate-oxide interface; threshold voltage; transconductance; Breakdown voltage; Degradation; Electric breakdown; Electron traps; MOSFETs; Plasma materials processing; Plasma simulation; Plasma sources; Stress; Threshold voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Design, 2001. Fourteenth International Conference on
Conference_Location
Bangalore
ISSN
1063-9667
Print_ISBN
0-7695-0831-6
Type
conf
DOI
10.1109/ICVD.2001.902705
Filename
902705
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