215GHz CMOS signal source based on a Maximum Gain Ring Oscillator topology

This paper introduces a Maximum Gain Ring Oscillator (MGRO) topology that maximizes the power gain achieved by the active devices using appropriately designed passive matching networks to maximize the frequency of oscillation. A design methodology is provided along with guidelines for the design of the passive matching network. In the absence of passive losses, the topology can oscillate at the fmax of the active devices. In the presence of passive loss, the losses can be taken into account in a closed-form fashion to maximize oscillation frequency. Based on this topology, an oscillator operating at approximately 107.5GHz is implemented using the 56-nm body-contacted devices of IBM´s 45nm SOI CMOS technology (fmax is about 200GHz). The second harmonic of this oscillation is extracted using a load-pull-optimized, extraction network. This topology can be generalized for the extraction of any harmonic from MGROs with different number of stages. The oscillator generates −14.4dBm of power at 216.2GHz while drawing 57.5mW of DC power. The modeling of 45nm SOI devices for millimeter-wave design is also described.