DocumentCode
2870456
Title
A 10b 160MS/s 84mW 1V Subranging ADC in 90nm CMOS
Author
Huber, Dan J. ; Chandler, Rodney J. ; Abidi, Asad A.
Author_Institution
California Univ., Los Angeles, CA
fYear
2007
fDate
11-15 Feb. 2007
Firstpage
454
Lastpage
615
Abstract
A 10b 160MS/S subranging ADC with THA is implemented in a 90nm digital CMOS process. Noise averaging and an auto-zeroed comparator are used in the fine converter to achieve low noise and offset at low power dissipation. The prototype converter achieves an ENOB of 9.1b for an 80MHz input and consumes 84mW from a 1V supply
Keywords
CMOS digital integrated circuits; analogue-digital conversion; comparators (circuits); 1 V; 10 bit; 80 MHz; 84 mW; 90 nm; auto-zeroed comparator; digital CMOS process; noise averaging; subranging analog-to-digital converter; Bandwidth; Capacitors; Clocks; Energy consumption; Low voltage; Power dissipation; Prototypes; Resistors; Sampling methods; Switches;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 2007. ISSCC 2007. Digest of Technical Papers. IEEE International
Conference_Location
San Francisco, CA
ISSN
0193-6530
Print_ISBN
1-4244-0853-9
Electronic_ISBN
0193-6530
Type
conf
DOI
10.1109/ISSCC.2007.373490
Filename
4242461
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