DocumentCode
2870768
Title
A 10,000-gate CMOS LSI processor
Author
Hoshikawa, R. ; Kikuchi, Hiroaki ; Baba, S. ; Sato, Seiki ; Kawato, K. ; Inui, N. ; Wada, O.
Author_Institution
Fujitsu, Ltd., Kawasaki, Japan
Volume
XXIII
fYear
1980
fDate
13-15 Feb. 1980
Firstpage
106
Lastpage
107
Abstract
A high-end silicon-gate CMOS microprocessor comprised of 10,000 gates, dissipating 130mW with a 400ns microinstruction cycle, will be reported. The average propagation delay time is 4-10ns/gate.
Keywords
CMOS process; CMOS technology; Integrated circuit interconnections; Large scale integration; Logic circuits; Microprocessors; Parity check codes; Propagation delay; Registers; Silicon;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference. Digest of Technical Papers. 1980 IEEE International
Conference_Location
San Francisco, CA, USA
Type
conf
DOI
10.1109/ISSCC.1980.1156134
Filename
1156134
Link To Document