DocumentCode
2870962
Title
A 5mA 0.6μm CMOS Miller-Compensated LDO Regulator with -27dB Worst-Case Power-Supply Rejection Using 60pF of On-Chip Capacitance
Author
Gupta, Vishal ; Rincón-Mora, Gabriel A.
Author_Institution
Georgia Inst. of Technol., Atlanta, GA
fYear
2007
fDate
11-15 Feb. 2007
Firstpage
520
Lastpage
521
Abstract
A 0.6mum 1.8V 5mA Miller-compensated SoC LDO regulator uses 60pF of capacitance to achieve a worst-case power-supply rejection of -27dB over 50MHz. The entire regulator is shielded from fluctuations in the supply using an NMOS cascode that is biased using a charge pump, voltage reference, and RC filters to maintain low dropout. The RC filter establishes a stable bias for the cascode without a significant impact on the efficiency or bandwidth of the LDO regulator.
Keywords
CMOS integrated circuits; RC circuits; controllers; power supply circuits; system-on-chip; 0.6 micron; 1.8 V; 5 mA; 6 pF; CMOS integrated circuit; Miller-compensated SoC LDO regulator; NMOS cascode; RC filters; charge pump; on-chip capacitance; voltage reference; worst-case power-supply rejection; Capacitance; Capacitors; Circuit noise; Filters; Fluctuations; MOS devices; Regulators; Resistors; Voltage; Working environment noise;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 2007. ISSCC 2007. Digest of Technical Papers. IEEE International
Conference_Location
San Francisco, CA
ISSN
0193-6530
Print_ISBN
1-4244-0852-0
Electronic_ISBN
0193-6530
Type
conf
DOI
10.1109/ISSCC.2007.373523
Filename
4242494
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