DocumentCode
2871245
Title
A 100ns 64K dynamic RAM using redundancy techniques
Author
Eaton, S. ; Wooten, D. ; Slemmer, W. ; Brady, James
Author_Institution
Immos Corporation, Colorado Springs, CO, USA
Volume
XXIV
fYear
1981
fDate
18-20 Feb. 1981
Firstpage
84
Lastpage
85
Abstract
A 64K×1 dynamic RAM with 100ns access time, fault-tolerant circuitry, high-speed serial data output and on-chip refresh circuitry, without the use of pin 1 for control, will be reported.
Keywords
Buffer storage; Content addressable storage; Counting circuits; DRAM chips; Decoding; Fuses; Random access memory; Read-write memory; Redundancy; Solid state circuits;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference. Digest of Technical Papers. 1981 IEEE International
Conference_Location
New York, NY, USA
Type
conf
DOI
10.1109/ISSCC.1981.1156166
Filename
1156166
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