Modified Leakage-Biased Domino Circuit with Low-Power and Low-Delay Characteristics

In this paper, a new domino logic structure whose architecture is based on a leakage biased (LB) domino circuit is introduced. The proposed technique improves the performance and the dynamic power consumption of the circuits. In addition, the number of transistors is reduced leading to a lower silicon area. Simulations are done for various circuits. Compared to the LB method, in a full adder circuit, the delay is reduced more than 25%; also, the dynamic and the static powers have reduced slightly.