Mitigating Partitioning, Routing, and Yield Concerns in 3D ICs by Multiplexing TSVs

Vertical stacking of integrated circuits has figured prominently in the International Technology Roadmap of Semiconductors. 3D ICs reduce global interconnect lengths, allow mixed technologies including DRAM and Flash, enables silicon reuse, and delivers power, performance and cost benefits. However, die-stacking requires inter-die interconnects known as through silicon vias (TSVs) that tend to be limited in number due to manufacturing and reliability concerns. This limitation constrains partitioning at the system level, affects routing area used by TSVs, and diminishes the benefit of vertical stacking. Here we present a means to increase the effective number of inter-die connections in 3D integrated circuits to mitigate such limitations. In the proposed solution, two signals originating in one die are multiplexed by the system clock and recovered by a combination of positive and negative edge-triggered flip-flops on the destination die. Also proposed is an extension where the signals need not originate on the same die. This method of multiplexing TSVs allows for the doubling of inter-die connections with very little area overhead or intrinsic performance overhead. Results show that this simple scheme unlocks the full potential of 3D in many designs which would not have been possible otherwise.