Power Efficient Multiplexer Using DLDFF Synchronous Counter

Data transition Look ahead D flip flop (DLDFF) consumes less power than a conventional D flip flop (DFF). A synchronous counter using Young´s counter architecture realized with DFF consumes less power than that with the conventional counter architecture, due to reduced transitions. Here, we propose a modified DLDFF which consumes less power. First, we design an 8 bit synchronous counter using the conventional counter architecture, with both the DFF and our proposed DLDFF. We observe that, as the size of the counter increases, the percentage increase in power consumption for the DLDFF is less than that of a counter realized with the DFF. Next, we design an 8 bit synchronous counter using our proposed DLDFF in the Young´s architecture. From the simulation results, we observe that, the counter using proposed DLDFF has 38% better power efficiency than a counter using DFF. As multiplexers find significant applications in the field of communications, we design an 8:1 multiplexer using the outputs of the counters as selection lines. We observe a 24% reduction in power consumption for the 8:1 multiplexer implemented with our proposed DLDFF.